A global router based on a multicommodity flow model
Integration, the VLSI Journal
Algorithmic aspects of three dimensional MCM routing
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance driven global routing and wiring rule generation for high speed PCBs and MCMs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Interconnect layout optimization under higher-order RLC model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A simple and effective greedy multilayer router for MCMs
Proceedings of the 1997 international symposium on Physical design
Performance driven global routing for standard cell design
Proceedings of the 1997 international symposium on Physical design
A New Timing-Driven Multilayer MCM/IC Routing Algorithm
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
MCG: a correct-by-design multichip module router with crosstalk avoidance
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
An iterative-improvement penalty-function-driven wire routing system
IBM Journal of Research and Development
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Improved global routing through congestion estimation
Proceedings of the 40th annual Design Automation Conference
Congestion reduction during placement with provably good approximation bound
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
2.5D system integration: a design driven system implementation schema
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Timing-constrained congestion-driven global routing
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Crosstalk Reduction in Area Routing
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Moment-driven coupling-aware routing methodology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Proceedings of the 2006 international symposium on Physical design
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In this paper we present a new global router appropriate for Multichip Module (MCM) and dense Printed Circuit Board (PCB) design, which utilizes a hybrid of the classical rip-up and reroute approach, and the more recent iterative deletion [9] method. The global router addresses performance issues by utilizing recent results in high performance interconnect design, while still effectively minimizing global congestion.With experimen ts on the maze-routing component of our global router, we show that the choice of routing cost functions can have a significant impact on final solution quality. The results of a number of previously proposed routers may be improved dramatically by adopting the cost functions we suggest here. W e also find little evidence of the “net ordering problem” when our cost functions and routing model are applied. The iterative deletion method is shown to improve global solution quality, particularly when high performance interconnect is required. We evaluate the performance of our global router by comparing the congestion of routes produced by our global router to those of a well known MCM router, V4R [14].Our global router, MINOTAUR, supports arbitrary numbers of routing layers, differing capacities for each layer, pre-existing congestion and obstacles, and high performance interconnect structures (including those which require variable width interconnect).