Improving over-the-cell channel routing in standard cell design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Algorithmic aspects of three dimensional MCM routing
DAC '94 Proceedings of the 31st annual Design Automation Conference
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Minimum crosstalk channel routing
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Performance driven multi-layer general area routing for PCB/MCM designs
DAC '98 Proceedings of the 35th annual Design Automation Conference
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A gridless multilayer router for standard cell circuits using CTM cells
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Via design rule consideration in multilayer maze routing algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing by new approximation algorithms for multicommodity flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Moment-driven coupling-aware routing methodology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
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Interconnect delay dominates system delay in modern circuits, and with reduced feature sizes, coupling capacitance and signal crosstalk have become significant issues. By spacing interconnect wires effectively, and avoiding long parallel runs, coupling can be reduced; with current routing methods, however, this is difficult to achieve. In this paper, we present a new approach to area routing. Rather than inserting routes sequentially (using a performance driven maze router), multiple candidate routes for each connection are generated; excess routes are then eliminated iteratively. Experiments show that we obtain substantial reductions in coupling capacitance, without sacrificing routing completion rates.