Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Benchmarks for layout synthesis—evolution and current status
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Requirements for models of achievable routing
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Unifying behavioral synthesis and physical design
Proceedings of the 37th Annual Design Automation Conference
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An exact algorithm for coupling-free routing
Proceedings of the 2001 international symposium on Physical design
Creating and exploiting flexibility in steiner trees
Proceedings of the 38th annual Design Automation Conference
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Improved global routing through congestion estimation
Proceedings of the 40th annual Design Automation Conference
Full-Chip Multilevel Routing for Power and Signal Integrity
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Crosstalk Reduction in Area Routing
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Empirical models for net-length probability distribution and applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HARP: hard-wired routing pattern FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Is probabilistic congestion estimation worthwhile?
Proceedings of the 2005 international workshop on System level interconnect prediction
Improved multilevel routing with redundant via placement for yield and reliability
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Moment-driven coupling-aware routing methodology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A novel framework for multilevel full-chip gridless routing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Multilevel full-chip gridless routing considering optical proximity correction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Simultaneous floorplanning and resource binding: a probabilistic approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Full-chip multilevel routing for power and signal integrity
Integration, the VLSI Journal
FastRoute: a step to integrate global routing into placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Escape routing for dense pin clusters in integrated circuits
Proceedings of the 44th annual Design Automation Conference
Archer: a history-driven global routing algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 international symposium on Physical design
MaizeRouter: engineering an effective global router
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Archer: a history-based global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact route matching algorithms for analog and mixed signal integrated circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Analog circuit shielding routing algorithm based on net classification
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extended global routing with RLC crosstalk constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient congestion mitigation using congestion-aware steiner trees and network coding topologies
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Traffic-predicting a routing algorithm using time series models
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part IV
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A prediction method of network traffic using time series models
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part III
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Predictable routing is the concept of using prespecified patterns to route a net. By doing this, we allow an more accurate prediction mechanism for metrics such as congestion and wirelength earlier in the design flow. Additionally, we can better plan the routes, insert buffers and perform wire sizing earlier. With comparable routing quality, we show that we can predictably route up to 80% of a selected subset of nets. Also, we introduce methods for finding a group of nets which can be predictably routed.