DAC '96 Proceedings of the 33rd annual Design Automation Conference
Performance driven multi-layer general area routing for PCB/MCM designs
DAC '98 Proceedings of the 35th annual Design Automation Conference
An efficient model for frequency-dependent on-chip inductance
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Improved global routing through congestion estimation
Proceedings of the 40th annual Design Automation Conference
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Crosstalk Reduction in Area Routing
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Transmission line synthesis via constrained multivariable optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect layout optimization under higher order RLC model for MCM designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A timing-constrained simultaneous global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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An underdamped signal response with a number of overshoots and undershoots may lead to false switching and increased settling time delay. This 'ringing' effect adversely affects the signal quality at the output and becomes a source of major concern at multi-GHz frequencies, as the self and mutual inductance of interconnects start playing a crucial role in the performance of a circuit. Reduction in wire length or minimization of coupling capacitance, the stronghold in many earlier routing techniques, may produce a routing solution suitable only at sub-GHz frequencies. In this paper, we propose a routing methodology that accounts for inductive and capacitive parasitics (self and mutual) of the interconnects in its cost function through a combination of second and third order central moments. A trade-off between signal delay and amount of ringing, quantified by second and third order central moments respectively, has been made, which generates a routing solution with the best compromise between ringing and delay for each net under a monotone signal response.