Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Layout tools for analog ICs and mixed-signal SoCs: a survey
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Efficient shield insertion for inductive noise reduction in nanometer technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SIAR: splitting-graph-based interactive analog router
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Configurable analog routing methodology via technology and design constraint unification
Proceedings of the International Conference on Computer-Aided Design
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Analog signals are more sensitive to crosstalk than digital signals, resulting in instability of analog circuits. To eliminate coupling, it is common practice to insert shielding wires on one or both sides of critical signals. In this paper, a novel analog circuit shielding routing algorithm based on net classification is proposed. Circuit performance requirements are transformed into geometric properties of nets according to the result of placement, and different shielding wire routing algorithms are designed to meet these geometric properties. A* algorithm is adopted to route the critical nets, and shielding wires are added at the same time. Maze algorithm is used to route the P/G nets and other general nets. Experimental results show that the router is efficient in routing and effective in reducing crosstalk. Although capacitive load and routing area increase, the resulting coupling is negligible and the circuit performance is significantly improved.