A current driven routing and verification methodology for analog applications
Proceedings of the 37th Annual Design Automation Conference
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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Proceedings of the 44th annual Design Automation Conference
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Proceedings of the 2009 international symposium on Physical design
Analog circuit shielding routing algorithm based on net classification
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routing analog ICs using a multi-objective multi-constraint evolutionary approach
Analog Integrated Circuits and Signal Processing
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As analog and mixed-signal (AMS) circuitry gains increasing portions in modern SoCs, automotive analog routing is becoming more and more important. This paper presents a fast real-time interactive analog router called SIAR based on a splitting graph. A key feature is that SIAR allows real-time interactions between the router and the designer. The designer can try different guiding points by moving the cursor in the user window and the router will show the corresponding routing solutions in real-time for the designer to select the most satisfactory one. To enable real-time interactions, we present a new splitting graph to represent the routing area, which greatly enhances the routing efficiency. Different design rules such as variable wire and via width/spacing are supported by the router. Moreover, SIAR supports different routing modes such as point-to-point, point-to-module and module-to-module. Experimental results show that SIAR obtains promising routing efficiency with upto 28.6x speedup and better routing solutions compared with the commercial router Laker as well as upto 108x speedup compared with a modified implication-graph-based gridless routing approach [13].