B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Block placement with symmetry constraints based on the O-tree non-slicing representation
Proceedings of the 37th Annual Design Automation Conference
Modeling non-slicing floorplans with binary trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Rectilinear block placement using B*-trees
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Using red-black interval trees in device-level analog placement with symmetry constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Placement with symmetry constraints for analog layout design using TCG-S
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Improved method of cell placement with symmetry constraints for analog IC layout design
Proceedings of the 2006 international symposium on Physical design
Analog placement with symmetry and other placement constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Symmetry within the sequence-pair representation in the context of placement for analog design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the exploration of the solution space in analog placement with symmetry constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog placement based on hierarchical module clustering
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Analog placement with common centroid and 1-D symmetry constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Thermal-driven analog placement considering device matching
Proceedings of the 46th Annual Design Automation Conference
Analog placement based on symmetry-island formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven analog placement considering boundary constraint
Proceedings of the 47th Design Automation Conference
Analog layout synthesis: recent advances in topological approaches
Proceedings of the Conference on Design, Automation and Test in Europe
Regularity-constrained floorplanning for multi-core processors
Proceedings of the 2011 international symposium on Physical design
SIAR: splitting-graph-based interactive analog router
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Heterogeneous B*-trees for analog placement with symmetry and regularity considerations
Proceedings of the International Conference on Computer-Aided Design
Fast analog layout prototyping for nanometer design migration
Proceedings of the International Conference on Computer-Aided Design
Routability-driven placement algorithm for analog integrated circuits
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Configurable analog routing methodology via technology and design constraint unification
Proceedings of the International Conference on Computer-Aided Design
Regularity-constrained floorplanning for multi-core processors
Integration, the VLSI Journal
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In this paper, we present the first amortized linear-time packing algorithm for the placement with symmetry constraints. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*-tree representation, we propose automatically symmetric-feasible B*-trees (ASF-B*-trees) to directly model the placement of a symmetry island. Unlike the previous works that can handle only 1D symmetry constraints, our ASF-B*-tree is the first in the literature to additionally consider 2D symmetry. We then present hierarchical B*-trees (HB*-trees) which can simultaneously optimize the placement with both symmetry islands and non-symmetry modules. Unlike the previous works, our approach can guarantee the close proximity of symmetry modules and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B*-tree or an HB*-tree is the same as that for a plain B*-tree (only amortized linear) and much faster than previous works which need at least loglinear time. Experimental results show that our approach achieves the best published quality and runtime efficiency for analog placement.