Correct-by-construction layout-centric retargeting of large analog designs
Proceedings of the 41st annual Design Automation Conference
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel symmetry-constraint generation for retargeting large analog layouts
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Proceedings of the International Conference on Computer-Aided Design
Configurable analog routing methodology via technology and design constraint unification
Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Efficient analog layout prototyping by layout reuse with routing preservation
Proceedings of the International Conference on Computer-Aided Design
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This paper presents an analog layout migration methodology to quickly provide multiple layouts while keeping similar or better circuit performance. Unlike previous works that often generate a single layout that has exactly the same topology with the original layout, this new migration algorithm is able to provide results with different aspect ratios. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Placement is performed from the bottom tree nodes to the root tree node. In each tree node, multiple placements for the subtree are recorded. All possible placements under the constraints are recorded in the root node. This algorithm has been successfully applied to a variable gain amplifier and a folded cascode operational amplifier migrating from UMC 90nm to UMC 65nm. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.