Performance-constrained template-driven retargeting for analog and RF layouts
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Integration, the VLSI Journal
A performance-constrained template-based layout retargeting algorithm for analog integrated circuits
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Analog layout retargeting using geometric programming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast analog layout prototyping for nanometer design migration
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.03 |
Layout parasitics can significantly affect the performance of analog integrated circuits (ICs). In this paper, a systematic method of optimizing an existing analog layout considering parasitics is presented for technology migration and performance retargeting. This method represents the locations of layout rectangle edges as variables and extracts circuit and layout integrity such as device symmetry, matching, and design rules as constraints. To ensure the desired circuit performance, bounds of layout parasitics are determined first. These bounds are used to constrain the layout geometries while retargeting existing high-quality layouts across technologies and specification sets. The problem is then solved by a graph-based algorithm combined with nonlinear optimization. The proposed method has been implemented in a parasitic-aware automatic layout optimization and retargeting tool (intellectual property reuse-based analog IC layout). Its efficiency and effectiveness are demonstrated by successfully retargeting operational amplifiers within 1 min of CPU time.