Generating Convex Polynomial Inequalities for Mixed 0–1 Programs
Journal of Global Optimization
Approximate formulae approach for efficient inductance extraction
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Performance of analog and RF integrated circuits is highly sensitive to layout parasitics. This paper presents a complete template-driven algorithm that automatically conducts performance-constrained parasitic-aware retargeting and optimization for analog and RF layouts. In order to ensure desired circuit performance even at high frequency, a lumped interconnect RLC model is deployed and geometric expressions of inductive parasitics are incorporated into optimization. Piecewise performance sensitivities with respect to layout parasitics are determined. Then the algorithm applies numeric performance sensitivities to control parasitic-related layout geometries by constructing performance constraints. The formulated problem is finally solved using a graph-based technique and mixed-integer nonlinear programming. The proposed method has been incorporated into a parasitic-aware automatic layout optimization and retargeting tool. It has been demonstrated to be effective and efficient especially when adapting layout design for new technologies or updated specifications.