Simulated annealing for VLSI design
Simulated annealing for VLSI design
Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome
Integration, the VLSI Journal
Using C to write portable CMOS VLSI module generators
EURO-DAC '94 Proceedings of the conference on European design automation
Effective Tcl/Tk programming: writing better programs with Tcl and Tk
Effective Tcl/Tk programming: writing better programs with Tcl and Tk
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Block placement with symmetry constraints based on the O-tree non-slicing representation
Proceedings of the 37th Annual Design Automation Conference
Analog Device-Level Layout Automation
Analog Device-Level Layout Automation
VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
Chip design: automation comes to analog
IEEE Spectrum - IEEE medal of honor Herwig Kogelnik
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the exploration of the solution space in analog placement with symmetry constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog layout generator for CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-constrained template-driven retargeting for analog and RF layouts
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Integration, the VLSI Journal
A performance-constrained template-based layout retargeting algorithm for analog integrated circuits
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Non-uniform multilevel analog routing with matching constraints
Proceedings of the 49th Annual Design Automation Conference
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Design of a linear power amplifier with ±1.5v power supply using ALADIN
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
LASER: layout-aware analog synthesis environment on laker
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Simultaneous analog placement and routing with current flow and current density considerations
Proceedings of the 50th Annual Design Automation Conference
Routing analog ICs using a multi-objective multi-constraint evolutionary approach
Analog Integrated Circuits and Signal Processing
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In this paper, a layout synthesis tool for the design of analog integrated circuits (ICs) is presented. This tool offers great flexibility that allows analog circuit designers to bring their special design knowledge and experiences into the synthesis process to create high-quality analog circuit layouts. Different from conventional layout systems that are limited to the optimization of single devices, our layout generation tool attempts to optimize more complex modules. This tool includes a complete tool suite that covers the following three major analog physical designs stages. 1) Module Generation: designers can develop and maintain their own technology- and application-independent module generators for subcircuits using an in-house developed description language. 2) Placement: a two-stage placement technique, tailored for the analog placement design, is proposed. In particular, this placement algorithm features a novel genetic placement stage followed by a fast simulated reannealing scheme. 3) Routing: the minimum-Steiner-tree-based global routing is developed, and it is actually integrated into the placement procedure to improve reliability and routability of the placement solutions. Following the global routing, a compaction-based constructive detailed routing finally completes the interconnection of the entire layout. Several testing circuits have been applied to demonstrate the design efficiency and the effectiveness of this tool. Experimental results show that this new layout tool is capable of producing high quality layouts comparable to those manually done by layout experts but with much less design time.