Retargeting of mixed-signal blocks for SoCs
Proceedings of the conference on Design, automation and test in Europe
Introduction to algorithms
Generating Convex Polynomial Inequalities for Mixed 0–1 Programs
Journal of Global Optimization
Convexification and Global Optimization in Continuous And
Convexification and Global Optimization in Continuous And
IPRAIL: intellectual property reuse-based analog IC layout automation
Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
Mathematical Programming: Series A and B
Chameleon ART: a non-optimization based analog design migration framework
Proceedings of the 43rd annual Design Automation Conference
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection
Proceedings of the 18th ACM Great Lakes symposium on VLSI
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Integrated Layout-Synthesis Approach for Analog ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to intrinsic intricacy, layout parasitics exhibit a significant impact on the performance of analog integrated circuits. In this paper a directly performance-constrained parasitic-aware automatic layout retargeting and optimization algorithm is presented. Unlike the conventional sensitivity analysis, a general central-difference based scheme using any simulator for sensitivity computation is deployed. We propose a piecewise sensitivity model to enforce more accurate sensitivity computation during parasitic optimization. Moreover, mixed-integer performance constraints due to parasitics are included in the formulated mixed integer nonlinear programming problem rather than through either indirect parasitic-bound constraints or inaccurate worst-case sensitivities. A graph technique and mixed-integer nonlinear programming are effectively combined to solve the formulated parasitic optimization problem. The automatically generated target layouts can satisfy performance constraints to ensure the desired specifications. The experimental results show that the proposed algorithm can achieve effective retargeting of analog circuits with less layout area and significant reduction in execution time.