Analog layout synthesis: recent advances in topological approaches
Proceedings of the Conference on Design, Automation and Test in Europe
Integration, the VLSI Journal
Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm
Integration, the VLSI Journal
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Context-dependent transformation of Pareto-optimal performance fronts of operational amplifiers
Analog Integrated Circuits and Signal Processing
LASER: layout-aware analog synthesis environment on laker
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Area optimization on fixed analog floorplans using convex area functions
Proceedings of the Conference on Design, Automation and Test in Europe
ITRS 2011 analog EDA challenges and approaches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Routing analog ICs using a multi-objective multi-constraint evolutionary approach
Analog Integrated Circuits and Signal Processing
Template coding with LDS and applications of LDS in EDA
Analog Integrated Circuits and Signal Processing
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In analog integrated circuit design, iterations between electrical and physical syntheses to counterbalance layout-induced performance degradations should be avoided as much as possible. One possible solution involves the integration of traditionally separated electrical and physical synthesis phases by including layout-induced effects right into the electrical synthesis phase in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of area or fulfillment of certain layout aspect ratio, among others) whose effects on the resulting parasitics are not usually considered during the electrical synthesis. In this paper, a layout-aware solution for analog cells that tackles both geometric and parasitic-aware electrical synthesis is proposed. Several design examples are provided.