Analog layout synthesis: recent advances in topological approaches

Authors:
H. Graeb;F. Balasa;R. Castro-Lopez;Y.-W. Chang;F. V. Fernandez;P.-H. Lin;M. Strasser
Affiliations:
Technische Universitaet Muenchen, Germany;Southern Utah University;Institute of Microelectronics of Sevilla, CSIC and University of Sevilla;National Taiwan University, Taiwan;Institute of Microelectronics of Sevilla, CSIC and University of Sevilla;National Taiwan University, Taiwan;Technische Universitaet Muenchen, Germany
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2009

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Abstract

This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks.