Generalized constraint generation in the presence of non-deterministic parasitics
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
General AC constraint transformation for analog ICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Module placement for analog layout using the sequence-pair representation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Layout tools for analog ICs and mixed-signal SoCs: a survey
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Layout-oriented synthesis of high performance analog circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Constraints space management for the layout of analog IC's
Proceedings of the conference on Design, automation and test in Europe
Device-level placement for analog layout: an opportunity for non-slicing topological representations
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Generation of Technology-Independent Retargetable Analog Blocks
Analog Integrated Circuits and Signal Processing
Synthesis of analog and mixed-signal integrated electronic circuits
Formal engineering design synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IPRAIL: intellectual property reuse-based analog IC layout automation
Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
A device-level placement with multi-directional convex clustering
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Multi-level placement with circuit schema based clustering in analog IC layouts
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Languages for system specification
Signal-path driven partition and placement for analog circuit
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Using red-black interval trees in device-level analog placement with symmetry constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Placement with symmetry constraints for analog layout design using TCG-S
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analog placement with symmetry and other placement constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
Analog placement with common centroid constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Symmetry-aware placement with transitive closure graphs for analog layout design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Symmetry constraint based on mismatch analysis for analog layout in SOI technology
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
On the verification of high-order constraint compliance in IC design
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Analog placement with common centroid and 1-D symmetry constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Constraint-driven design: the next step towards analog design automation
Proceedings of the 2009 international symposium on Physical design
Analog placement based on symmetry-island formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic generation of hierarchical placement rules for analog integrated circuits
Proceedings of the 19th international symposium on Physical design
Performance-constrained template-driven retargeting for analog and RF layouts
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Analog layout synthesis: recent advances in topological approaches
Proceedings of the Conference on Design, Automation and Test in Europe
Integration, the VLSI Journal
A performance-constrained template-based layout retargeting algorithm for analog integrated circuits
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Non-uniform multilevel analog routing with matching constraints
Proceedings of the 49th Annual Design Automation Conference
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Simultaneous analog placement and routing with current flow and current density considerations
Proceedings of the 50th Annual Design Automation Conference
Routing analog ICs using a multi-objective multi-constraint evolutionary approach
Analog Integrated Circuits and Signal Processing
Template coding with LDS and applications of LDS in EDA
Analog Integrated Circuits and Signal Processing
Efficient analog layout prototyping by layout reuse with routing preservation
Proceedings of the International Conference on Computer-Aided Design
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A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach