A VHDL-AMS compiler and architecture generator for behavioral synthesis of analog systems
DATE '99 Proceedings of the conference on Design, automation and test in Europe
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents our experience on high-level synthesis of Σ - Δ analog to digital converters (ADC) from VHDL-AMS descriptions. The proposed VHDL-AMS subset for synthesis is discussed. The subset has the composition semantics, so that specifications offer enough insight into the system structure for automated architecture generation and optimization. A case study for the synthesis of a fourth order Σ - Δ ADC is detailed. Compared to similar work, the method is more flexible in tackling new designs, and more tolerant to layout parasitic.