Introduction to algorithms
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Module placement for analog layout using the sequence-pair representation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Device-level placement for analog layout: an opportunity for non-slicing topological representations
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Modeling non-slicing floorplans with binary trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Languages for system specification
Aladin: A Layout Synthesys Tool for Analog Integrated Circuits
Analog Integrated Circuits and Signal Processing
Using red-black interval trees in device-level analog placement with symmetry constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Placement with symmetry constraints for analog layout design using TCG-S
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Analog placement with symmetry and other placement constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analog placement based on novel symmetry-island formulation
Proceedings of the 44th annual Design Automation Conference
Analog placement with common centroid constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analog placement based on hierarchical module clustering
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Analog placement with common centroid and 1-D symmetry constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Analog placement based on symmetry-island formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven analog placement considering boundary constraint
Proceedings of the 47th Design Automation Conference
Regularity-constrained floorplanning for multi-core processors
Proceedings of the 2011 international symposium on Physical design
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A corner stitching compliant B*-tree representation and its applications to analog placement
Proceedings of the International Conference on Computer-Aided Design
Heterogeneous B*-trees for analog placement with symmetry and regularity considerations
Proceedings of the International Conference on Computer-Aided Design
Practical placement and routing techniques for analog circuit designs
Proceedings of the International Conference on Computer-Aided Design
Routability-driven placement algorithm for analog integrated circuits
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Performance-driven analog placement considering monotonic current paths
Proceedings of the International Conference on Computer-Aided Design
Double patterning lithography-aware analog placement
Proceedings of the 50th Annual Design Automation Conference
Regularity-constrained floorplanning for multi-core processors
Integration, the VLSI Journal
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The ordered tree (O-tree) representation has recently gained much interest in layout design automation. Different from previous topological representations of non-slicing floorplans, the O-tree representation is simpler, needs linear computation effort to generate a corresponding layout, and exhibits a smaller upper-bound of possible configurations. This paper addresses the problem of handling symmetry constraints in the context of the O-tree representation. This problem arises in analog placements, where symmetry is often used to match layout-induced parasitics and to balance thermal couplings in differential circuits. The good performance of our placement tool dealing with several analog designs taken from industry proves the effectiveness of our technique.