Simulated annealing for VLSI design
Simulated annealing for VLSI design
Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome
Integration, the VLSI Journal
Effective Tcl/Tk programming: writing better programs with Tcl and Tk
Effective Tcl/Tk programming: writing better programs with Tcl and Tk
Block placement with symmetry constraints based on the O-tree non-slicing representation
Proceedings of the 37th Annual Design Automation Conference
A common mode feedback structure for differential OpAmps using NMOS depletion transistors
Analog Integrated Circuits and Signal Processing
VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
Chip design: automation comes to analog
IEEE Spectrum - IEEE medal of honor Herwig Kogelnik
A Novel Analog Module Generator Environment
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Symmetry within the sequence-pair representation in the context of placement for analog design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog layout generator for CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits
Proceedings of the 50th Annual Design Automation Conference
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This paper presents a layout synthesis tool called ALADIN for analog integrated circuits. It is developed especially for analog circuit designers who can bring their special knowledge and experience into the synthesis process to create high quality layouts. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators of sub-circuits. Based on the thorough study of simulated annealing and genetic algorithm applications in the analog module placement, a genetic placement approach with simulated annealing and a very fast simulated re-annealing placement approach have been developed. A two-stage placement technique is proposed. Analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. This tool is integrated into commercial software with convenient interfaces provided. The benefit of ALADIN providing layouts comparable to expert manual ones is demonstrated with several circuits showing its competition compared to other existing tools.