B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Block placement with symmetry constraints based on the O-tree non-slicing representation
Proceedings of the 37th Annual Design Automation Conference
Placement with symmetry constraints for analog layout design using TCG-S
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Double patterning technology friendly detailed routing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Analog placement based on symmetry-island formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A matching based decomposer for double patterning lithography
Proceedings of the 19th international symposium on Physical design
Double patterning layout decomposition for simultaneous conflict and stitch minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Double patterning lithography aware gridless detailed routing with innovative conflict graph
Proceedings of the 47th Design Automation Conference
Regularity-oriented analog placement with diffusion sharing and well island generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A corner stitching compliant B*-tree representation and its applications to analog placement
Proceedings of the International Conference on Computer-Aided Design
Practical placement and routing techniques for analog circuit designs
Proceedings of the International Conference on Computer-Aided Design
Symmetry within the sequence-pair representation in the context of placement for analog design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Double patterning lithography (DPL) is one of the most promising solutions for the 28nm technology node and beyond. The main idea of DPL is to decompose the layout into two sub-patterns and manufacture the layout by two masks. In addition to traditional analog design constraints, the pre-coloring constraint should also be considered, in which patterns of critical or sensitive modules have predefined masks before layout decomposition to reduce mismatches. In this paper, we present the first work that considers DPL during analog placement and simultaneously minimizes area, wirelength, and DPL conflicts. We first propose an extended conflict graph (ECG) to represent the relation between patterns of analog modules and apply an integer linear programming (ILP) formulation to determine the orientation of each module and the color of each pattern for conflict minimization. ILP reduction schemes are proposed to further reduce the runtime. Finally, we present a three-stage flow and DPL-aware perturbations to obtain desired solutions. Experimental results show that the proposed flow can effectively and efficiently reduce area, wirelength, and DPL conflicts.