Multi-level placement with circuit schema based clustering in analog IC layouts

Authors:
Takashi Nojima;Xiaoke Zhu;Yasuhiro Takashima;Shigetoshi Nakatake;Yoji Kajitani
Affiliations:
SII EDA Technologies Inc., Kitakyushu, Fukuoka, Japan;SII EDA Technologies Inc., Kitakyushu, Fukuoka, Japan;The University of Kitakyushu, Kitakyushu, Fukuoka, Japan;The University of Kitakyushu, Kitakyushu, Fukuoka, Japan;The University of Kitakyushu, Kitakyushu, Fukuoka, Japan
Venue:
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Year:
2004

Citing 8
Cited 5

Rectangle-packing-based module placement

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Module placement on BSG-structure and IC layout applications

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Module placement for analog layout using the sequence-pair representation

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
FAST-SP: a fast algorithm for block placement based on sequence pair

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Analog Device-Level Layout Automation

Analog Device-Level Layout Automation
Using red-black interval trees in device-level analog placement with symmetry constraints

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Automation of IC layout with analog constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSI module placement based on rectangle-packing by the sequence-pair

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Constraint-free analog placement with topological symmetry structure

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Analog placement based on hierarchical module clustering

Proceedings of the 45th annual Design Automation Conference
Regularity-oriented analog placement with diffusion sharing and well island generation

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A corner stitching compliant B*-tree representation and its applications to analog placement

Proceedings of the International Conference on Computer-Aided Design
Practicality on placement given by optimality of packing

Proceedings of the 2013 ACM international symposium on International symposium on physical design

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper aims at developing an automated device-level placement for analog circuit design which achieves comparable quality to manual designs by experts. It extracts a set of clusters from a circuit schema as experts do. We provide a multi-level placement based on the Sequence-Pair by relaxing the shape of clusters from rectangles and allowing boundaries of clusters to be 'jagged'. The quality of placement is evaluated by a multi-objective according to an expert's guideline. We adopt a multi-step simulated annealing to balance a trade-off between the objectives. In experiments, we tested the placement for industrial examples. Our tool attained placements better than those by manual on the average by 10.8% and 6.8% with respect to area and net-length, respectively. It also achieved 1/730 layout time compared with the time by manual.