Optimal orientations of cells in slicing floorplan designs
Information and Control
An optimal algorithm for floorplan area optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Area minimization for hierarchical floorplans
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An analytical algorithm for placement of arbitrarily sized rectangular blocks
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Hybrid floorplanning based on partial clustering and module restructuring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Cluster refinement for block placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
VLSI/PCB placement with obstacles based on sequence-pair
Proceedings of the 1997 international symposium on Physical design
A layout approach to monolithic microwave IC
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Sequence-pair based placement method for hard/soft/pre-placed modules
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Rectilinear block placement using sequence-pair
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Topology constrained rectilinear block packing for layout reuse
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Slicing floorplans with pre-placed modules
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Arbitrary rectilinear block packing based on sequence pair
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Slicing floorplans with range constraint
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Arbitrary convex and concave rectilinear block packing using sequence-pair
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Post-placement residual-overlap removal with minimal movement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Slicing tree is a complete floorplan representation
Proceedings of the conference on Design, automation and test in Europe
Automatic datapath tile placement and routing
Proceedings of the conference on Design, automation and test in Europe
A new encoding scheme for rectangle packing problem
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Faster and more accurate wiring evaluation in interconnect-centric floorplanning
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Revisiting floorplan representations
Proceedings of the 2001 international symposium on Physical design
Integrated power supply planning and floorplanning
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
VLSI block placement using less flexibility first principles
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Texture mapping progressive meshes
Proceedings of the 28th annual conference on Computer graphics and interactive techniques
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
Proceedings of the 2002 international symposium on Physical design
Twin binary sequences: a non-redundant representation for general non-slicing floorplan
Proceedings of the 2002 international symposium on Physical design
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
Proceedings of the 39th annual Design Automation Conference
Least squares conformal maps for automatic texture atlas generation
Proceedings of the 29th annual conference on Computer graphics and interactive techniques
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Floorplan representations: Complexity and connections
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transistor placement for noncomplementary digital VLSI cell synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Genetic Algorithm for VLSI Floorplanning
PPSN VI Proceedings of the 6th International Conference on Parallel Problem Solving from Nature
Physical Design of CMOS Chips in Six Easy Steps
SOFSEM '00 Proceedings of the 27th Conference on Current Trends in Theory and Practice of Informatics
Rectilinear block placement using B*-trees
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Rectilinear Block Placement Using B*-Trees
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Aware Interface Synthesis for Bus-Based SoC Designs
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Deterministic VLSI block placement algorithm using less flexibility first principle
Journal of Computer Science and Technology
An area-optimality study of floorplanning
Proceedings of the 2004 international symposium on Physical design
Transforming 3D mesh surfaces into images by parameterization
Integrated image and graphics technologies
A device-level placement with multi-directional convex clustering
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Robust fixed-outline floorplanning through evolutionary search
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Multi-level placement with circuit schema based clustering in analog IC layouts
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Temporal floorplanning using 3D-subTCG
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Placement constraints in floorplan design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
3D module placement for congestion and power noise reduction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Partitioning and placement for buildable QCA circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the 42nd annual Design Automation Conference
Physical Design for 3D System on Package
IEEE Design & Test
Floorplan design for multi-million gate FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A robust detailed placement for mixed-size IC designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A fixed-die floorplanning algorithm using an analytical approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast buffer planning and congestion optimization in interconnect-driven floorplanning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Simultaneous floorplanning and buffer block planning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An improved P-admissible floorplan representation based on Corner Block List
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast floorplanning by look-ahead enabled recursive bipartitioning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Placement with symmetry constraints for analog layout design using TCG-S
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Floorplanning for 3-D VLSI design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Interconnect estimation without packing via ACG floorplans
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Substrate noise modeling in early floorplanning of MS-SOCs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
Improved method of cell placement with symmetry constraints for analog IC layout design
Proceedings of the 2006 international symposium on Physical design
Robust mixed-size placement under tight white-space constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
3D floorplanning with thermal vias
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Microarchitectural floorplanning under performance and thermal tradeoff
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Module placement for fault-tolerant microfluidics-based biochips
Proceedings of the 41st annual Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Floorplan repair using dynamic whitespace management
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A revisit to floorplan optimization by Lagrangian relaxation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analog placement with symmetry and other placement constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Decoupling capacitor planning and sizing for noise and leakage reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
NoC-Based FPGA: Architecture and Routing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Optimizing wirelength and routability by searching alternative packings in floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multi-bend bus driven floorplanning
Integration, the VLSI Journal
A simultaneous bus orientation and bused pin flipping algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analog placement with common centroid constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Constraint-free analog placement with topological symmetry structure
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Bus-aware microarchitectural floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A unified methodology for power supply noise reduction in modern microarchitecture design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Effective decap insertion in area-array SoC floorplan design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Solving modern mixed-size placement instances
Integration, the VLSI Journal
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Analog placement with common centroid and 1-D symmetry constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A Relocation Method for Circuit Modifications
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Parallel Simulated Annealing Approach for Floorplanning in VLSI
ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
IEEE Transactions on Multimedia
Topology/floorplan/pipeline co-design of cascaded crossbar bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus via reduction based on floorplan revising
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus-pin-aware bus-driven floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Hybrid algorithm for floorplanning using B*-tree representation
IITA'09 Proceedings of the 3rd international conference on Intelligent information technology application
Decoupling capacitor planning with analytical delay model on RLC power grid
Proceedings of the Conference on Design, Automation and Test in Europe
Configurable multi-product floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
UFO: unified convex optimization algorithms for fixed-outline floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Physical design techniques for optimizing RTA-induced variations
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
TCG: a transitive closure graph-based representation for general floorplans
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-objective module placement for 3-d system-on-package
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient package pin-out planning with system interconnects optimization for package-board codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ITEM: inter-texture error measurement for 3D meshes
Proceedings of the 16th International Conference on 3D Web Technology
Thermal-aware bus-driven floorplanning
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Thermal signature: a simple yet accurate thermal index for floorplan optimization
Proceedings of the 48th Design Automation Conference
A quick generation method of sequence pair for block placement
ICCS'05 Proceedings of the 5th international conference on Computational Science - Volume Part III
An improved algorithm for sequence pair generation
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part I
Practical placement and routing techniques for analog circuit designs
Proceedings of the International Conference on Computer-Aided Design
Routability-driven placement algorithm for analog integrated circuits
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Applying the sequence-pair representation to optimal facility layout designs
Operations Research Letters
Optimal binary representation of mosaic floorplans and baxter permutations
FAW-AAIM'12 Proceedings of the 6th international Frontiers in Algorithmics, and Proceedings of the 8th international conference on Algorithmic Aspects in Information and Management
Bus-driven floorplanning with bus pin assignment and deviation minimization
Integration, the VLSI Journal
Efficient packing of arbitrarily shaped charts for automatic texture atlas generation
EGSR'11 Proceedings of the Twenty-second Eurographics conference on Rendering
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Practicality on placement given by optimality of packing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design
Journal of Electronic Testing: Theory and Applications
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The first and the most critical stage in VLSI layout design is the placement, the background of which is the rectangle packing problem: Given many rectangular modules of arbitrary size, place them without overlapping on a layer in the smallest bounding rectangle. Since the variety of the packing is infinite (two- dimensionally continuous) many, the key issue for successful optimization is in the introduction of a P-admissible solution space, which is a finite set of solutions at least one of which is optimal. This paper proposes such a solution space where each packing is represented by a pair of module name sequences. Searching this space by simulated annealing, hundreds of modules could be successfully packed as demonstrated. Combining a conventional wiring method, the biggest MCNC benchmark ami49 is challenged.