Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Analysis and optimization of thermal issues in high-performance VLSI
Proceedings of the 2001 international symposium on Physical design
Microarchitecture evaluation with physical planning
Proceedings of the 40th annual Design Automation Conference
Profile-guided microarchitectural floorplanning for deep submicron processor design
Proceedings of the 41st annual Design Automation Conference
Multi-bend bus driven floorplanning
Proceedings of the 2005 international symposium on Physical design
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Proceedings of the 42nd annual Design Automation Conference
Integrated floorplanning with buffer/channel insertion for bus-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal optimization in multi-granularity multi-core floorplanning
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Bus via reduction based on floorplan revising
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Thermal-aware bus-driven floorplanning
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Bus-driven floorplanning with bus pin assignment and deviation minimization
Integration, the VLSI Journal
Bus-driven floorplanning with thermal consideration
Integration, the VLSI Journal
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In this paper we present the first bus-aware microarchitectural floorplanning. Our goal is to study the impact of bus routability on other important floorplanning objectives including area, performance, power, and thermal. We developed a fast performance-aware bus routing algorithm, which is integrated into the floorplanning engine to ensure routability while optimizing other conflicting objectives. Our related experiments performed on high performance processors show that we obtain 100% routability at the cost of minimal increase on area, performance, and power objectives under thermal constraint.