Clock rate versus IPC: the end of the road for conventional microarchitectures
Proceedings of the 27th annual international symposium on Computer architecture
Timing driven placement using physical net constraints
Proceedings of the 38th annual Design Automation Conference
Microarchitecture evaluation with physical planning
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 15 - Volume 16
Floorplan assisted data rate enhancement through wire pipelining: a real assessment
Proceedings of the 2005 international symposium on Physical design
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Proceedings of the 42nd annual Design Automation Conference
Joint exploration of architectural and physical design spaces with thermal consideration
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Microarchitecture evaluation with floorplanning and interconnect pipelining
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Microarchitectural floorplanning under performance and thermal tradeoff
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 2006 international symposium on Low power electronics and design
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Adaptive Latency-Insensitive Protocols
IEEE Design & Test
Microarchitecture configurations and floorplanning co-optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature aware microprocessor floorplanning considering application dependent power load
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Bus-aware microarchitectural floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Thermal optimization in multi-granularity multi-core floorplanning
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Topology/floorplan/pipeline co-design of cascaded crossbar bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-aware floorplanning exploration for 3D multi-core architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Exploiting local logic structures to optimize multi-core SoC floorplanning
Proceedings of the Conference on Design, Automation and Test in Europe
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As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communication within a single cycle, thus decaying the performance scalability substantially. An effective floorplanning algorithm can no longer ignore the information of dynamic communication patterns of applications. In this paper, using the profile information acquired at the architecture/microarchitecture level, we propose a "profile-guided microarchitectural floorplanner" that considers both the impact of wire delay and the architectural behavior, namely the inter-module communication, to reduce the latency of frequent routes inside a processor and to maintain performance scalability. Based on our simulation results, the profile-guided method shows a 5% to 40% average IPC improvement when clock frequency is fixed. From the perspective of instruction throughput(in BIPS), our floorplanner is much more scalable than a conventional wire length based floorplanner.