Zero-cycle loads: microarchitecture support for reducing load latency
Proceedings of the 28th annual international symposium on Microarchitecture
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
On-chip decoupling capacitor optimization using architectural level prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Validating the Intel® Pentium® 4 Microprocessor
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Inductive Noise Reduction at the Architectural Level
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage
Proceedings of the 30th annual international symposium on Computer architecture
Proceedings of the 2003 international symposium on Low power electronics and design
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
Profile-guided microarchitectural floorplanning for deep submicron processor design
Proceedings of the 41st annual Design Automation Conference
Exploiting Resonant Behavior to Reduce Inductive Noise
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the 2004 international symposium on Low power electronics and design
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization
HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
Microarchitectural floorplanning under performance and thermal tradeoff
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
DCG: deterministic clock-gating for low-power microprocessor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous power supply planning and noise avoidance in floorplan design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified methodology for power supply noise reduction in modern microarchitecture design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A modular 3d processor for flexible product design and technology migration
Proceedings of the 5th conference on Computing frontiers
Proceedings of the 37th annual international symposium on Computer architecture
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Architecture and Code Optimization (TACO)
AUDIT: Stress Testing the Automatic Way
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
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Power delivery is a growing reliability concern in micropro- cessors as the industry moves toward feature-rich, power- hungrier designs. To battle the ever-aggravating power con- sumption, modern microprocessor designers or researchers propose and apply aggressive power-saving techniques in the form of clock-gating and/or power-gating in order to oper- ate the processor within a given power envelope. These tech- niques, however, often lead to high-frequency current varia- tions, which can stress the power delivery system and jeop- ardize reliability due to inductive noise (L\frac{{di}} {{dt}} ) in the power supply network. To counteract these issues, modern mi- croprocessors are designed to operate under the worst-case current assumption by deploying adequate decoupling capac- itance. With the trend of lower supply voltage and increased leakage power and current consumption, designing a proces- sor for the worst case is becoming less appealing. In this paper, we propose a new dynamic inductive-noise controlling mechanism at the microarchitectural level that will limit the on-die current demand within predefined bounds, regardless of the native power and current characteristics of running applications. By dynamically monitoring the access patterns of microarchitectural modules, our mechanism can effectively limit simultaneous switching activity of close-by modules, thereby leveling voltage ringing at local power-pins. Compared to prior art, our di/dt controller is the first that takes the processor's floorplan as well as its power-pin dis- tribution into account to provide a finer-grained control with minimal performance degradation. Based on the evaluation results using 2D floorplans, we show that our techniques can significantly improve inductive noise induced by current de- mand variation and reduce the average current variability by up to 7 times with an average performance overhead of 4.0%.