Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
ReVive: cost-effective architectural support for rollback recovery in shared-memory multiprocessors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage
Proceedings of the 30th annual international symposium on Computer architecture
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Performance implications of single thread migration on a chip multi-core
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Timing analysis in presence of supply voltage and temperature variations
Proceedings of the 2006 international symposium on Physical design
Techniques for Multicore Thermal Management: Classification and New Exploration
Proceedings of the 33rd annual international symposium on Computer Architecture
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
ReCycle:: pipeline adaptation to tolerate process variation
Proceedings of the 34th annual international symposium on Computer architecture
A study of thread migration in temperature-constrained multicores
ACM Transactions on Architecture and Code Optimization (TACO)
Efficient power modeling and software thermal sensing for runtime temperature monitoring
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards a software approach to mitigate voltage emergencies
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Predictive dynamic thermal management for multicore systems
Proceedings of the 45th annual Design Automation Conference
EVAL: Utilizing processors with variation-induced timing errors
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Thread motion: fine-grained power management for multi-core systems
Proceedings of the 36th annual international symposium on Computer architecture
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications
Proceedings of the Conference on Design, Automation and Test in Europe
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Process, Voltage, and Temperature (PVT) variations can significantly degrade the performance benefits expected from next nanoscale technology. The primary circuit implication of the PVT variations is the resultant timing emergencies. In a multi-core processor running multiple programs, variations create spatial and temporal unbalance across the processing cores. Most prior schemes are dedicated to tolerating PVT variations individually for a single core, but ignore the opportunity of leveraging the complementary effects between variations and the intrinsic variation unbalance among individual cores. We find that the notorious delay impacts from different variations are not necessary aggregated. Cores with mild variations can share the violent workload from cores suffering large variations. If operated correctly, variations on different cores can help mitigating each other and result in a variation-mild environment. In this paper, we propose Timing Emergency Aware Thread Migration (TEA-TM), a delay sensor-based scheme to reduce system timing emergencies under PVT variations. Fourier transform and frequency domain analysis are conducted to provide the insights and the potential of the PVT co-optimization scheme. Experimental results show on average TEA-TM can help save up to 24% throughput loss, at the same time improve the system fairness by 85%.