The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Breathing life into a paper tiger (keynote session)
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
Exploiting Resonant Behavior to Reduce Inductive Noise
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the 2004 international symposium on Low power electronics and design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Controlling inductive cross-talk and power in off-chip buses using CODECs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
VLIW instruction scheduling for minimal power variation
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the 37th annual international symposium on Computer architecture
Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause noise margins to decrease, while increasing current and frequency makes supply noise injection larger, especially noise caused by inductance in the supply lines. Creating power distribution systems is one of the key challenges in modern chip design. Decoupling capacitance helps reduce inductance effects, but there is often a peak in the supply impedance that occurs at a resonant frequency caused roughly by the package inductance and the chip decoupling capacitors. This frequency is on the order of 100MHz, which is much lower than the operating frequency of the processor. We propose pipeline damping, an architectural technique which controls instruction issue to guarantee bounds on current variation around the frequency of the supply resonance, thus reducing the resulting supply noise. Damping is a cheaper alternative to expensive, circuit-based noise-reduction techniques. We make the fundamental observation that limiting the current flow change (di) within resonant time period (dt) controls di/dt without large performance loss. Damping guarantees bounds on current variation while allowing processor current to increase or decrease to the magnitude required to maintain performance. Our results show that a damped processor guarantees a 33% reduction in the worst-case current variation with an average performance degradation of 7% and average energy delay of 1.09 compared to an undamped processor.