Dynamic voltage scaling on a low-power microprocessor
Proceedings of the 7th annual international conference on Mobile computing and networking
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
Deterministic Clock Gating for Microprocessor Power Reduction
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage
Proceedings of the 30th annual international symposium on Computer architecture
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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We propose an integrated architectural/physical planning approach to reduce the power supply noise due to current surge in high performance, general-purpose, clock-gated microprocessors. The proposed approach combines dynamic selection of functional units on-the-fly, dynamic issue width scaling and physical planning with soft module, to balance the current demand across layout. Experimental results show that the proposed approach could reduce the peak noise by 6.54% and consequently, the decoupling capacitance requirement by 21.8%. The degradation in IPC (Instruction Per Cycle) due to the selection logic and issue width scaling is only 1.86e-7 (without increasing clock cycle period) in 0.18mm technology.