A microarchitectural-level step-power analysis tool
Proceedings of the 2002 international symposium on Low power electronics and design
On achieving balanced power consumption in software pipelined loops
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Microarchitectural dI/dt Control
IEEE Design & Test
PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage
Proceedings of the 30th annual international symposium on Computer architecture
Proceedings of the 2003 international symposium on Low power electronics and design
Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting Resonant Behavior to Reduce Inductive Noise
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the 2004 international symposium on Low power electronics and design
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
VLIW instruction scheduling for minimal power variation
ACM Transactions on Architecture and Code Optimization (TACO)
Towards a software approach to mitigate voltage emergencies
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A modular 3d processor for flexible product design and technology migration
Proceedings of the 5th conference on Computing frontiers
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack
Proceedings of the 46th Annual Design Automation Conference
A microarchitecture-based framework for pre- and post-silicon power delivery analysis
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A cross-layer approach to heterogeneity and reliability
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Thermal-aware voltage droop compensation for multi-core architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 37th annual international symposium on Computer architecture
Eliminating voltage emergencies via software-guided code transformations
ACM Transactions on Architecture and Code Optimization (TACO)
An event-guided approach to reducing voltage noise in processors
Proceedings of the Conference on Design, Automation and Test in Europe
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated di/dt stressmark generation for microprocessor power delivery networks
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
ACM Transactions on Architecture and Code Optimization (TACO)
Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
AUDIT: Stress Testing the Automatic Way
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications
Proceedings of the Conference on Design, Automation and Test in Europe
Estimation based power and supply voltage management for future RF-powered multi-core smart cards
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Eagle-eye: a near-optimal statistical framework for noise sensor placement
Proceedings of the International Conference on Computer-Aided Design
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As the power consumption of modern high-performance microprocessors increases beyond 100W, power becomes an increasingly important design consideration. This paper presents a novel technique to simulate power supply voltage variation as a result of varying activity levels within the microprocessor when executing typical software. The voltage simulation capability may be added to existing microarchitecture simulators that determine the activities of each functional block on a clock-by-clock basis. We then discuss how the same technique can be implemented in logic on the microprocessor die to enable real-time computation of current consumption and power supply voltage. When used in a feedback loop, this logic makes it possible to control the microprocessor's activities to reduce demands on the power delivery system. With on-die voltage computation and di/dt control, we show that a significant reduction in power supply voltage variation may be achieved with little performance loss or average power increase.