A low power SRAM using auto-backgate-controlled MT-CMOS
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
The YAGS branch prediction scheme
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
A Thermal-Aware Superscalar Microprocessor
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Reducing power density through activity migration
Proceedings of the 2003 international symposium on Low power electronics and design
Design and implementation of the POWER5™ microprocessor
Proceedings of the 41st annual Design Automation Conference
Single-vDD and single-vT super-drowsy techniques for low-leakage high-performance instruction caches
Proceedings of the 2004 international symposium on Low power electronics and design
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Heat Stroke: Power-Density-Based Denial of Service in SMT
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Pin: building customized program analysis tools with dynamic instrumentation
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
A performance-conserving approach for reducing peak power consumption in server systems
Proceedings of the 19th annual international conference on Supercomputing
Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Performance implications of single thread migration on a chip multi-core
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Challenges of data center thermal management
IBM Journal of Research and Development - POWER5 and packaging
POWER4 system microarchitecture
IBM Journal of Research and Development
Predictive dynamic thermal management for multicore systems
Proceedings of the 45th annual Design Automation Conference
Analytical results for design space exploration of multi-core processors employing thread migration
Proceedings of the 13th international symposium on Low power electronics and design
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Throughput optimal task allocation under thermal constraints for multi-core processors
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 7th ACM international conference on Computing frontiers
Efficient calibration of thermal models based on application behavior
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Proceedings of the 37th annual international symposium on Computer architecture
Hardware/software co-design architecture for thermal management of chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Temperature-aware task scheduling algorithm for soft real-time multi-core systems
Journal of Systems and Software
Task Allocation and Migration Algorithm for Temperature-Constrained Real-Time Multi-Core Systems
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Microvisor: a runtime architecture for thermal management in chip multiprocessors
Transactions on High-Performance Embedded Architectures and Compilers IV
A multi-agent framework for thermal aware task migration in many-core systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fairness-aware scheduling on single-ISA heterogeneous multi-cores
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
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Temperature has become an important constraint in high-performance processors, especially multicores. Thread migration will be essential to exploit the full potential of future thermally constrained multicores. We propose and study a thread migration method that maximizes performance under a temperature constraint, while minimizing the number of migrations and ensuring fairness between threads. We show that thread migration brings important performance gains and that it is most effective during the first tens of seconds following a decrease of the number of running threads.