Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Hybrid Architectural Dynamic Thermal Management
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Performance implications of single thread migration on a chip multi-core
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synergistic temperature and energy management in GALS processor architectures
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A study of thread migration in temperature-constrained multicores
ACM Transactions on Architecture and Code Optimization (TACO)
Addressing thermal nonuniformity in SMT workloads
ACM Transactions on Architecture and Code Optimization (TACO)
GOP-level dynamic thermal management in MPEG-2 decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 7th ACM international conference on Computing frontiers
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Exploiting narrow-width values for thermal-aware register file designs
Proceedings of the Conference on Design, Automation and Test in Europe
Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Low-overhead core swapping for thermal management
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Recent thermal management techniques for microprocessors
ACM Computing Surveys (CSUR)
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A thermal-aware technique is proposed to minimize the performance impact when thermal/power control mechanism is triggered. This technique, called thermal-aware microprocessor (TAM), uses on-chip thermal sensors to detect hot-spots within the microprocessor die. There is a secondary pipeline within the core. It is architecturally simple with ultra low power implementation. This secondary pipeline has two main functions: 1. thermal relieve; 2. ultra low power implementation for certain mobile environment (such as any where any time email connect function). When temperature exceeds a given threshold, the core superscalar pipelines are clock-gated while a secondary in-order pipeline is engaged. Since the secondary pipeline consumes much less power, it will have a much lower temperature, and therefore, it will provide a temporary thermal relieve to the core pipelines when the thermal/power mechanism is triggered. This relief reduces energy loss due to leakage, prevents overheating to improve product reliability, and eases cost for thermal solutions. The TAM can also combine with other low power techniques such voltage scaling to achieve ultra low power for mobile. In the paper, we compared TAM with two other thermal/power control techniques, namely dynamic clock disabling and dynamic frequency scaling. The TAM exhibits an 11.4% improvement in overall energy-performance metric with 4.6% increase in area.