Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines

Authors:
Anahita Shayesteh;Eren Kursun;Tim Sherwood;Suleyman Sair;Glenn Reinman
Affiliations:
Computer Science Department, University of California, Los Angeles;Computer Science Department, University of California, Los Angeles;Computer Science Department, University of California, Santa Barbara;Department of Electrical and Computer Engineering, North Carolina State University;Computer Science Department, University of California, Los Angeles
Venue:
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Year:
2005

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Abstract

Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature management techniques. To combat these trends, we explore the use of core swapping on a microcore architecture, a deeply decoupled processor core with larger structures factored out as helper engines. The microcore architecture presents an ideal platform for core swapping thanks to helper engines that maintain the state of each process in a shared fabric surrounding the cores, reducing the impact of core swapping 43% on average while showing promising thermal reduction. It also has favorable performance when compared to other thermal management techniques. Furthermore, we evaluate alternative approaches to spending the area overhead of the additional microcore, including larger microcores, CMP cores, and SMT cores with different thermal management techniques.