Low-overhead core swapping for thermal management

Authors:
Eren Kursun;Glenn Reinman;Suleyman Sair;Anahita Shayesteh;Tim Sherwood
Affiliations:
Computer Science Department, University of California, Los Angeles;Computer Science Department, University of California, Los Angeles;Department of Electrical and Computer Engineering, North Carolina State University;Computer Science Department, University of California, Los Angeles;Department of Computer Science, University of California, Santa Barbara
Venue:
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Year:
2004

Citing 17
Cited 7

A comprehensive instruction fetch mechanism for a processor supporting speculative execution

MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References

IEEE Transactions on Computers
Highly accurate data value prediction using hybrid predictors

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A scalable front-end architecture for fast instruction delivery

ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Wattch: a framework for architectural-level power analysis and optimizations

Proceedings of the 27th annual international symposium on Computer architecture
Predictor-directed stream buffers

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
A static power model for architects

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
A framework for dynamic energy efficiency and temperature management

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs

Proceedings of the 38th annual Design Automation Conference
Reducing the complexity of the register file in dynamic superscalar processors

Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Automatically characterizing large scale program behavior

Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Instruction-Level Distributed Processing

Computer
A Thermal-Aware Superscalar Microprocessor

ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Temperature-aware microarchitecture

Proceedings of the 30th annual international symposium on Computer architecture
Reducing power density through activity migration

Proceedings of the 2003 international symposium on Low power electronics and design
Dynamic Thermal Management for High-Performance Microprocessors

HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture

GOP-level dynamic thermal management in MPEG-2 decoding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines

HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Performance and energy efficient cache migrationapproach for thermal management in embedded systems

Proceedings of the 20th symposium on Great lakes symposium on VLSI
Hardware/software co-design architecture for thermal management of chip multiprocessors

Proceedings of the Conference on Design, Automation and Test in Europe
REEact: a customizable virtual execution manager for multicore platforms

VEE '12 Proceedings of the 8th ACM SIGPLAN/SIGOPS conference on Virtual Execution Environments
Microvisor: a runtime architecture for thermal management in chip multiprocessors

Transactions on High-Performance Embedded Architectures and Compilers IV
Towards scalable arithmetic units with graceful degradation

ACM Transactions on Embedded Computing Systems (TECS)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature management techniques. To combat these trends, we evaluate the thermal efficiency of the microcore architecture, a deeply decoupled processor core with larger structures factored out as helper engines. We further investigate activity migration (core swapping) as a means of controlling the thermal profile of the chip in this study. Specifically, the microcore architecture presents an ideal platform for core swapping thanks to helper engines that maintain the state of each process in a shared fabric surrounding the cores. This results in significantly reduced migration overhead, enabling seamless swapping of cores. Our results show that our thermal mechanisms outperform traditional Dynamic Thermal Management (DTM) techniques by reducing the performance hit caused by slowing/swapping of cores. Our experimental results show that the microcore architecture has 86% fewer thermally critical cycles compared to a conventional monolithic core.