Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
ICET: a complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
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Proceedings of the 37th Annual Design Automation Conference
Electrothermal analysis of VLSI systems
Electrothermal analysis of VLSI systems
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis and optimization of thermal issues in high-performance VLSI
Proceedings of the 2001 international symposium on Physical design
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Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Timing Minimization by Statistical Timing hMetis-based Partitioning
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Placement Method Targeting Predictability Robustness and Performance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Analog Integrated Circuits and Signal Processing
Elmore model for energy estimation in RC trees
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Self-heating-aware optimal wire sizing under Elmore delay model
Proceedings of the conference on Design, automation and test in Europe
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
IEICE - Transactions on Information and Systems
Evaluating the effects of temperature gradients and currents nonuniformity in on-chip interconnects
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Analog Integrated Circuits and Signal Processing
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Non-uniform temperature profiles along global interconnect lines in high-performance ICs can significantly impact the performance of these lines. This paper presents a detailed analysis and modeling of the interconnect performance degradation due to non-uniform temperature profiles that exist along their lengths, which in turn arise due to the thermal gradients in the underlying substrate. A non-uniform temperature-dependent distributed RC interconnect delay model is proposed for the first time. The model has been applied to a wide variety of interconnect layouts and temperature distributions to quantify the impact on signal integrity issues including clock skew fluctuations.