Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs
Proceedings of the 38th annual Design Automation Conference
System level leakage reduction considering the interdependence of temperature and leakage
Proceedings of the 41st annual Design Automation Conference
A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Cross Layer Error Exploitation for Aggressive Voltage Scaling
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
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Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage Vdd and temperature on memory performance and their interrelationships. We propose a Temperature- and Reliability- Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware Vdd selection using TRAM can reduce the total power dissipation by up to 2.5X while attaining an identical predefined limit on errors.