Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
The need for a full-chip and package thermal model for thermally optimized IC designs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Temperature-Dependent Optimization of Cache Leakage Power Dissipation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Microarchitectural floorplanning under performance and thermal tradeoff
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Microarchitecture-level leakage reduction with data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Floorplan driven leakage power aware IP-based SoC design space exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Temperature-aware leakage minimization technique for real-time systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Efficient power modeling and software thermal sensing for runtime temperature monitoring
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Thermal-aware task scheduling at the system software level
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Statistical power profile correlation for realistic thermal estimation
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
FEKIS: a fast architecture-level thermal analyzer for online thermal regulation
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe
Closed-loop modeling of power and temperature profiles of FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance-aware thermal management via task scheduling
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 7th ACM international conference on Computing frontiers
Dynamic thermal management for single and multicore processors under soft thermal constraints
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
TRAM: a tool for temperature and reliability aware memory design
Proceedings of the Conference on Design, Automation and Test in Europe
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the International Conference on Computer-Aided Design
A novel methodology to reduce leakage power in CMOS complementary circuits
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
On the fundamentals of leakage aware real-time DVS scheduling for peak temperature minimization
Journal of Systems Architecture: the EUROMICRO Journal
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The high leakage devices in nanometer technologies as well as the low activity rates in system-on-a-chip (SOC) contribute to the growing significance of leakage power at the system level. We first present system-level leakage-power modeling and characteristics and discuss ways to reduce leakage for caches. Considering the interdependence between leakage power and temperature, we then discuss thermal runaway and dynamic power and thermal management (DPTM) to reduce power and prevent thermal violations. We show that a thermal-independent leakage model may hide actual failures of DPTM. Finally, we present voltage scaling considering DPTM for different packaging options. We show that the optimal Vdd for the best throughput may be smaller than the largest Vdd allowed by the given packaging platform, and that advanced cooling techniques can improve throughput significantly.