ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Proceedings of the 2001 international symposium on Physical design
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization
Proceedings of the conference on Design, automation and test in Europe - Volume 1
System level leakage reduction considering the interdependence of temperature and leakage
Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Compact thermal modeling for temperature-aware design
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2004 international symposium on Low power electronics and design
Proceedings of the 2004 international symposium on Low power electronics and design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Parameterized transient thermal behavioral modeling for chip multiprocessors
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
Integration, the VLSI Journal
Parameterized architecture-level dynamic thermal models for multicore microprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient additive statistical leakage estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A linear statistical analysis for full-chip leakage power with spatial correlation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper proposes a new statistical response surface based power estimation technique. The new approach is able to include a number of parameters such as multiple Vdd, multiple Vth and gate sizing parameters. It has both deterministic ability and statistical ability. The deterministic ability allows the new model to provide optimal design parameters for power reduction. The statistical ability can be used to model the process variation impact on power.