Modeling and analysis of leakage power considering within-die process variations

Authors:
Ashish Srivastava;Robert Bai;David Blaauw;Dennis Sylvester
Affiliations:
University of Michigan, Ann Arbor, MI;University of Michigan, Ann Arbor, MI;University of Michigan, Ann Arbor, MI;University of Michigan, Ann Arbor, MI
Venue:
Proceedings of the 2002 international symposium on Low power electronics and design
Year:
2002

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Abstract

We describe the impact of process variation on leakage power for a 0.18mm CMOS technology. We show that variability, manifested in Ldrawn, Tox, and Nsub, can drastically affect the leakage current. We first present Monte Carlo-based simulation results for leakage current in various CMOS gates when the process parameters are varied both individually and concurrently. We then derive an analytical model to estimate the mean and standard deviation of the leakage current as a function of the process parameter distributions. We demonstrate that the results of the analytical model match well with Monte-Carlo simulations and also show the statistical mean leakage current is significantly different from the leakage predicted using a nominal case file.