Leakage power characterization considering process variations

Authors:
Jose L. Rosselló;Carol de Benito;Sebastià Bota;Jaume Segura
Affiliations:
Electronic Technology Group, Universitat Illes Balears, Palma de Mallorca, Spain;Electronic Technology Group, Universitat Illes Balears, Palma de Mallorca, Spain;Electronic Technology Group, Universitat Illes Balears, Palma de Mallorca, Spain;Electronic Technology Group, Universitat Illes Balears, Palma de Mallorca, Spain
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

We present a novel technique to accurately describe the leakage power in CMOS nanometer Integrated Circuits (ICs) considering process variations. The model predicts a leakage power increment due to process variations with high accuracy. It is shown that leakage increases considerably as channel length variations become larger due to technology scaling. The present work also describes accurately the dependence of leakage dispersion with process variations. The model developed shows that, even if channel length variations are kept small the leakage dispersion is considerably large. Finally, the concept of “Hot Gates” (HGs) is introduced, showing that HGs will be an important reliability factor in near future nanometer technologies.