Elmore model for energy estimation in RC trees
Proceedings of the 43rd annual Design Automation Conference
Impact of Thermal Gradients on Clock Skew and Testing
IEEE Design & Test
A self-adjusting clock tree architecture to cope with temperature variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
SACTA: a self-adjusting clock tree architecture for adapting to thermal-induced delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage power characterization considering process variations
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
An efficient method for analyzing on-chip thermal reliability considering process variations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
As chips become faster, the need to test them at their intended speed of operation has been recognized. High-speed operation, together with the higher switching activity typically induced during test, can result in a die-thermal distribution significantly different from that achieved during normal operation. Differences in thermal map distribution between normal- and test-mode operations give rise to a nonuniform impact on the relative path delay within logic blocks. The impact of test-induced hot spots may artificially slow down non-critical paths or speed-up critical ones with respect to the clock making the whole die to fail (pass) delay testing for a good (bad) part. The non-uniform thermal-induced delay is especially important for clock circuitry, the most critical block, which is impacted even if exact zero-skew clock routing algorithms are adopted. In this work we analyze the impact of thermal map temperature changes on the clock delay identifying a new delay-fault mechanism. We propose a technique to minimize the impact of different test- and normal-mode thermal maps by making the clock tree speed independent of temperature gradients. This technique allows applying confidently delay test patterns to the die regardless of the thermalmap test-induced modification.