Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Process variation aware clock tree routing
Proceedings of the 2003 international symposium on Physical design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
A multiple level network approach for clock skew minimization with process variations
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process
IEEE Transactions on Computers
WITHIN DIE THERMAL GRADIENT IMPACT ON CLOCK-SKEW: ANEW TYPE OF DELAY-FAULT MECHANISM
ITC '04 Proceedings of the International Test Conference on International Test Conference
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffered clock tree sizing for skew minimization under power and thermal budgets
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Electro-thermal coupling analysis methodology for RF circuits
Microelectronics Journal
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It is a well-known phenomenon that test-mode switching activity and power consumption can exceed that of mission mode. Thus, testing can induce localized heating and temperature gradients with deleterious results. The authors quantify this problem and propose a novel design scheme to circumvent it.