Impact of Thermal Gradients on Clock Skew and Testing
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
Journal of Electronic Testing: Theory and Applications
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Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel ...