Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Screening MinVDD Outliers Using Feed-Forward Voltage Testing
ITC '02 Proceedings of the 2002 IEEE International Test Conference
MINVDD Testing for Weak CMOS ICs
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
CMOS Electronics: How It Works, How It Fails
CMOS Electronics: How It Works, How It Fails
A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Low Voltage Test in Place of Fast Clock in DDSI Delay Test
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model
ITC '04 Proceedings of the International Test Conference on International Test Conference
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
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As CMOS IC feature sizes shrink down to the nanometer regime, the need for more efficient test methods capable of dealing with new failure mechanisms increases. Advances in this domain require a detailed knowledge of these failure physical properties and the development of appropriated test methods. Several works have shown the relative increase of resistive defects (both opens and shorts), and that they mainly affect circuit timing rather than impacting its static DC behavior. Defect evolution, together with the increase of parameter variations, represents a serious challenge for traditional delay test methods based on fixed time delay limit setting. One alternative to deal with variation relies on adopting correlation where test limits for one parameter are settled based on its correspondence to other circuit variables. In particular, the correlation of circuit delay to reduced VDD has been proposed as a useful test method. In this work we investigate the merits of this technique for future technologies where variation is predicted to increase, analyzing the possibilities of detecting resistive shorts and opens.