Compact static power model of complex CMOS gates

Authors:
Jose L. Rosselló;Sebastià Bota;Jaume Segura
Affiliations:
Electronic Technology Group, Universitat de les Illes Balears, Palma de Mallorca, Spain;Electronic Technology Group, Universitat de les Illes Balears, Palma de Mallorca, Spain;Electronic Technology Group, Universitat de les Illes Balears, Palma de Mallorca, Spain
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

Citing 1
Cited 1

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ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

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PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

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Abstract

We present a compact model to estimate quickly and accurately the leakage power in CMOS nanometer Integrated Circuits (ICs). The model has similar accuracy than SPICE and represents an important improvement with respect to previous works. It has been developed to be used for fast and accurate estimation and optimization of the standby power dissipated by large circuits.