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This paper presents an efficient approach to statistical leakage analysis (SLA) that can estimate the arbitrary n-sigma leakage currents of the VLSI system for the probability density function (PDF) of a lognormal distribution. Unlike existing SLA approaches, the proposed method uses deterministic cell leakage models and gate-level deterministic leakage analysis, and thus, provides significantly reduced analysis complexity. Providing the n-sigma chip leakage current for the PDF of WM-based SLA with a computational complexity of O(N), where N is the number of cells in a chip, the proposed approach is a promising candidate for the analysis of recent technology (comprising billions of logic cells in a chip) to address the high-complexity of conventional approaches to SLA. Compared to conventional WM-based SLA, when the value of n was 5.1803, 3.6022, and 2.8191, the average absolute errors of n-sigma chip leakage current exhibited by the proposed approach were 5.08%, 4.73%, and 4.45%, respectively.