Early power exploration—a World Wide Web application
DAC '96 Proceedings of the 33rd annual Design Automation Conference
System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
State-based power analysis for systems-on-chip
Proceedings of the 40th annual Design Automation Conference
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Robust extraction of spatial correlation
Proceedings of the 2006 international symposium on Physical design
Considering process variations during system-level power analysis
Proceedings of the 2006 international symposium on Low power electronics and design
A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 47th Design Automation Conference
On hierarchical statistical static timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient statistical leakage analysis using deterministic cell leakage models
Microelectronics Journal
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System-level power analysis is commonly used in modern SoC design processes to evaluate power consumption at early design phases. With the increasing variations in manufacturing, the statistical characteristics of parameters are also incorporated in the state-of-the-art methods. However, the spatial correlation between modules still remains as a challenge for system-level statistical power analysis where power models generated from individual modules are used for analysis efficiency or IP protection. In this paper, we propose a novel method to extract variation-aware and correlation-inclusive leakage power models for fast and accurate system-level analysis. For each individual module we generate a power model with different correlation information specified by the module vendor or customer. The local random variables in the power models are replaced by the corresponding ones at system level to reconstruct the correlation between modules so that the accuracy of system-level analysis is guaranteed. Experimental results show that our method are very accurate while being 1000X faster than Monte Carlo simulation and 70X -- 100X faster than the flattened full chip statistical leakage analysis.