IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Prediction of interconnect pattern density distribution: derivation, validation, and applications
Proceedings of the 2003 international workshop on System-level interconnect prediction
Design and optimization of MOS current mode logic for parameter variations
Proceedings of the 14th ACM Great Lakes symposium on VLSI
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Design and optimization of MOS current mode logic for parameter variations
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Self-Compensating Design for Focus Variation
Proceedings of the 42nd annual Design Automation Conference
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design
Proceedings of the 42nd annual Design Automation Conference
CAD tools for variation tolerance
Proceedings of the 42nd annual Design Automation Conference
Bringing Manufacturing into Design via Process-Dependent SPICE Models
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the 43rd annual Design Automation Conference
Variability-aware device optimization under ION and leakage current constraints
Proceedings of the 2006 international symposium on Low power electronics and design
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Statistical model order reduction for interconnect circuits considering spatial correlations
Proceedings of the conference on Design, automation and test in Europe
A novel criticality computation method in statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Clustering based pruning for statistical criticality computation under process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variational capacitance modeling using orthogonal polynomial method
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Statistical timing analysis of flip-flops considering codependent setup and hold times
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 5th conference on Computing frontiers
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 13th international symposium on Low power electronics and design
An analog on-chip adaptive body bias calibration for reducing mismatches in transistor pairs
Proceedings of the conference on Design, automation and test in Europe
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs
Microelectronics Journal
A parametric approach for handling local variation effects in timing analysis
Proceedings of the 46th Annual Design Automation Conference
Fast and accurate statistical criticality computation under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Adaptive sampling for efficient failure probability analysis of SRAM cells
Proceedings of the 2009 International Conference on Computer-Aided Design
Design and optimization of MOS current mode logic for parameter variations
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Proceedings of the 20th symposium on Great lakes symposium on VLSI
DSP-driven self-tuning of RF circuits for process-induced performance variability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical leakage estimation based on sequential addition of cell leakage currents
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Using randomization to cope with circuit uncertainty
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical analysis of hold time violations
Journal of Computational Electronics
Dynamic power estimation for deep submicron circuits with process variation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Variation-aware placement with multi-cycle statistical timing analysis for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variational capacitance extraction and modeling based on orthogonal polynomial method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MOS current mode circuits: analysis design and variability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware layout-driven scheduling for performance yield optimization
Proceedings of the International Conference on Computer-Aided Design
A statistical model of logic gates for Monte Carlo simulation including on-chip variations
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
A test and calibration strategy for adjustable RF circuits
Analog Integrated Circuits and Signal Processing
Efficient statistical leakage analysis using deterministic cell leakage models
Microelectronics Journal
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Process-induced parameter variations cause performance actuations and are an important consideration in the design of high performance digital ICs. Until recently, it was sufficient to model die-to-die shifts in device (active) and wire (passive) parameters, leading to a natural worst-case design methodology [1, 2].In the deep-submicron era, however, within-die variations in these same device and wire parameters become just as important. In fact, current integrated circuits are large enough that variations within the die are as large as variations from die-to-die. Furthermore, while die-to-die shifts are substantially independent of the design, within-die variations are profoundly influenced by the detailed physical implementation of the IC.This changes the fundamental view of process variability from something that is imposed on the design by the fabrication process to something that is co-generated between the design and the process. This paper starts by examining the sources and historical trends in device and wire variability, distinguishing between inter-die and intra-die variations, and proposes techniques for design for variability (DOV) in the presence of both types of variations.