Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Proceedings of the 42nd annual Design Automation Conference
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Process variation aware OPC with variational lithography modeling
Proceedings of the 43rd annual Design Automation Conference
Standard cell characterization considering lithography induced variations
Proceedings of the 43rd annual Design Automation Conference
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Characterizing process variation in nanometer CMOS
Proceedings of the 44th annual Design Automation Conference
Analytical yield prediction considering leakage/performance correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Device parameter variations exhibit an increasingly serious impact on analog and mixed-signal circuit behavior. In this paper, we propose a novel fully-analog on-chip adaptive body bias calibration method, for efficiently reducing mismatches in transistor pairs. We present three circuit implementations which achieve a mismatch reduction between 61% and 73% in terms of standard deviation.