MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Analysis and design of low-phase-noise ring oscillators
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
MOSFET Modeling and Bsim3 User's Guide
MOSFET Modeling and Bsim3 User's Guide
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Optimum Power/Performance Pipeline Depth
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Power-optimal pipelining in deep submicron technology
Proceedings of the 2004 international symposium on Low power electronics and design
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Design of Integrated Circuits for Optical Communications
Design of Integrated Circuits for Optical Communications
A symmetric mos current-mode logic universal gate for high speed applications
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Low-power mixed-signal CVNS-based 64-bit adder for media signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nanopower subthreshold MCML in submicrometer CMOS technology
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
An efficient delay model for MOS current-mode logic automated design and optimization
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low-power tri-state buffer in MOS current mode logic
Analog Integrated Circuits and Signal Processing
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The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are gaining attention by circuit designers to provide shorter design cycles and faster time to market. This paper provides designers with an insight to the different tradeoffs involved in the design of MCML circuits to efficiently and systematically design MCML circuits. A comprehensive analytical formulation for the design parameters of MCML circuits using the BSIM3v3 model is introduced. In addition, a closed-form expression for the noise margin of two-level MCML circuits is derived. In order to verify the validity of the analytical formulations, an automated design methodology for MCML circuits is proposed to overcome the complexities of the design process. The effectiveness of the design methodology and the accuracy of the analytical formulations are tested by designing several MCML benchmarks built in a 0.18-µm CMOS technology. The error in the required performance in the designed circuits is within 11% when compared to HSPICE simulations. A worst case parameter variations modeling is presented to investigate the impact of variations on MCML circuits as well as designing MCML circuits for variability. Finally, the impact of variations on MCML circuits is investigated with technology scaling and different circuit architectures.