A symmetric mos current-mode logic universal gate for high speed applications

Authors:
Osman Musa Abdulkarim;Maitham Shams
Affiliations:
Carleton University, Ottawa, ON, Canada;Carleton University, Ottawa, ON, Canada
Venue:
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Year:
2007

Citing 2
Cited 1

Design of Analog CMOS Integrated Circuits

Design of Analog CMOS Integrated Circuits
MOS current mode circuits: analysis design and variability

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

An efficient delay model for MOS current-mode logic automated design and optimization

IEEE Transactions on Circuits and Systems Part I: Regular Papers

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Abstract

Mos Current Mode Logic (MCML) is a low-noise alternative toconventional CMOS for mixed-signal applications. The standard MCML Universal Gate is a utility circuit that can implement the basic logic operations (AND/NAND/OR/NOR). The asymmetric topology of the universal gates, however, reduces its operation frequency significantly. In this paper, a modified version of the standard universal gate is analyzed to quantify its advantages and drawbacks. When compared to the differential-pair universal gate, the modified topology has better output waveform, higher operation frequency and lower switching noise for the same power dissipation.