Nonlinear programming: theory, algorithms, and applications
Nonlinear programming: theory, algorithms, and applications
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Intelligent Optimisation Techniques: Genetic Algorithms, Tabu Search, Simulated Annealing and Neural Networks
A symmetric mos current-mode logic universal gate for high speed applications
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Design of a MCML Gate Library Applying Multiobjective Optimization
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
MOS current mode circuits: analysis design and variability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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MOS current-mode logic (MCML) is a low-noise alternative to CMOS logic. The lack of MCML automation tools, however, has deterred designers from applying MCML to complex digital functions. This paper presents an efficient MCML optimization program that can be used to properly size MCML gates. The delay model accuracy is adjusted by fitting measured gate delays by means of technology-dependent parameters. For an N number of logic gates, the proposed mathematical program has reduced the number of variables to N + 1, in comparison to 7 N + 1 in the most recent work on this topic. The program has been implemented to efficiently optimize a 4-bit ripple carry adder and an 8-bit decoder in 0.18-µm CMOS technology.